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ASAHI KASEI
[AK4641]
AK4641
16-Bit CODEC with Bluetooth Interface
GENERAL DESCRIPTION The AK4641 is targeted at PDA and other low-power, small size applications. It features a 16bit Stereo CODEC with a built-in Microphone-Amplifier and 16bit Mono CODEC for Bluetooth Interface. Input circuits include Microphone-Amplifier and ALC (Auto Level Control) circuit. The AK4641 is available in a 36pin QFN, utilizing less board space than competitive offerings. FEATURES 1. Recording Function of 16bit Stereo CODEC * Mono Input * 2 to 1 Selector (Internal and External MIC) * 1st MIC Amplifier: +20dB or 0dB * 2nd Amplifier with ALC: +27.5dB -8dB, 0.5dB Step * ADC Performance: S/(N+D): 81dB, S/N: 86dB * Sampling Rate: 7kHz 48kHz * Audio Interface Format: I2S, 16bit MSB justified 2. Playback Function of 16bit Stereo CODEC * Digital De-emphasis Filter (tc=50/15s, fs=32kHz, 44.1kHz, 48kHz) * Digital Volume (0dB -127dB, 0.5dB Step, Mute) * 5 Band Equalizer * Stereo Line Output - Performance: S/(N+D): 86dB, S/N: 90dB * Mono Line Output - Differential Output - Performance: S/(N+D): 86dB, S/N: 93dB * AUX Input - Differential Input - +24dB -21dB, 3dB step * Sampling Rate: 7kHz 48kHz * Audio Interface Format: I2S, 16bit MSB justified, 16bit LSB justified 3. 16bit Mono CODEC * Analog Mix Path for Bluetooth Interface * Sample Rate: 8kHz 16kHz * Audio Interface Format: Short/Long Frame, I2S, 16bit MSB justified 4. Power Management 5. Master Clock: 1.792MHz 12.288MHz 6. Control mode: I2C Bus 7. Ta = -10 70C 8. Power Supply: 2.6V 3.6V (typ. 3.3V) 9. Power Supply Current: 17mA 10. Package: 36pin QFN (0.5mm pitch)
MS0301-E-00 -1-
2004/05
ASAHI KASEI
[AK4641]
Block Diagram
AVSS AVDD MICOUT
PMMIC
DVSS DVDD
AIN TST2 TST1
PMADC
MPE MPI INT
MIC Power Supply
MIC Power Supply
EXT MDT
0.075 x AVDD
MIC-AMP 0dB or 20dB
ALC1 (IPGA)
ADC
HPF
MCLK PDN
ATT PMMO
ATT
MOUT+
ATT
Stereo CODEC Audio Interface
LRCK BICK SDTO
MOUTPMLO PMDAC
SDTI
LOUT
DAC
ROUT
PMMIX PMMO2
5Band DATT SMUTE EQ
DSP and uP
SCL
MOUT2
Control Register
SDA
PMAD2
BBICK
PMAUX
ADC
HPF Mono CODEC Audio I/F
BSYNC BSDTO BSDTI
AUXIN+
Volume
AUXIN-
PMDA2
Bluetooth Module
DAC
VCOM
PLL
VCOC
BVDD
BVSS
Figure 1. Block Diagram
MS0301-E-00 -2-
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ASAHI KASEI
[AK4641]
Ordering Guide
AK4641VN AKD4641 -10 +70C 36pin QFN (0.5mm pitch) Evaluation board for AK4641
Pin Layout (36pin QFN)
MICOUT
AUXIN+
AUXIN-
MOUT+
MOUT- 29
36
35
34
33
32
31
30
MPE MPI INT VCOM AVSS AVDD BVDD BVSS VCOC
28
LOUT
MDT
EXT
AIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
27 26 25 24
ROUT MOUT2 TST2 BBICK BSYNC BSDTO BSDTI DVSS DVDD
Top View
23 22 21 20 19
SDTO
MS0301-E-00 -3-
MCLK
LRCK
TST1
BICK
SDTI
PDN
SDA
SCL
2004/05
ASAHI KASEI
[AK4641]
PIN/FUNCTION
Function MIC Power Supply Pin for External Microphone MIC Power Supply Pin for Internal Microphone Internal Microphone Input Pin (Mono Input) Common Voltage Output Pin, 0.45*AVDD 4 VCOM O Bias voltage of ADC inputs and DAC outputs. 5 AVSS Analog Ground Pin 6 AVDD Analog Power Supply Pin 7 BVDD Power Supply Pin for 16bit Mono CODEC of Bluetooth I/F 8 BVSS Ground Pin for 16bit Mono CODEC of Bluetooth I/F 9 VCOC O PLL Loop Filter Pin for 16bit Mono CODEC of Bluetooth I/F Power-Down Mode Pin 10 PDN I "H": Power up, "L": Power down reset and initializes the control register. 11 TST1 I Test Pin. Connect to DVSS. 12 SCL I Control Data Clock Pin 13 SDA I/O Control Data Input Pin 14 SDTI I Audio Serial Data Input Pin 15 SDTO O Audio Serial Data Output Pin 16 LRCK I Input/Output Channel Clock Pin 17 BICK I Audio Serial Data Clock Pin 18 MCLK I External Master Clock Input Pin 19 DVDD Digital Power Supply Pin 20 DVSS Digital Ground Pin 21 BSDTI I Serial Data Input Pin for 16bit Mono CODEC of Bluetooth I/F 22 BSDTO O Serial Data Output Pin for 16bit Mono CODEC of Bluetooth I/F 23 BSYNC I Sync Signal Pin for 16bit Mono CODEC of Bluetooth I/F 24 BBICK I Serial Data Clock Pin for 16bit Mono CODEC of Bluetooth I/F 25 TST2 I Test Pin. Connect to AVSS. 26 MOUT2 O Mono Line Output 2 Pin 27 ROUT O Rch Stereo Line Output Pin 28 LOUT O Lch Stereo Line Output Pin 29 MOUT- O Mono Line Negative Output Pin 30 MOUT+ O Mono Line Positive Output Pin 31 AUX IN- I Mono AUX Negative Input Pin 32 AUX IN+ I Mono AUX Positive Input Pin 33 AIN I Analog Input Pin 34 MICOUT O Microphone Analog Output Pin 35 MDT I Microphone Detect Pin (Internal pull down by 500k) 36 EXT I External Microphone Input Pin (Mono Input) Note: All input pins except analog input pins (INT, EXT, AIN, AUXIN+, AUXIN-, MDT) should not be left floating. No. 1 2 3 Pin Name MPE MPI INT I/O O O I
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below. Classification Pin Name Analog Input INT, AUXIN+, AUXIN-, AIN, MDT, EXT MPE, MPI, MOUT2, ROUT, LOUT, MOUT-, MOUT+, Analog Output MICOUT Digital Input BSDTI, BSYNC, BBICK Digital Output BSDTO
Setting These pins should be open. These pins should be open. These pins should be connected to DVSS. These pins should be open.
MS0301-E-00 -4-
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ASAHI KASEI
[AK4641]
ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, BVSS =0V; Note 1) Parameter Symbol min Power Supplies: Analog AVDD -0.3 Digital DVDD -0.3 16bit Mono CODEC BVDD -0.3 |AVSS - DVSS| (Note 2) GND1 |AVSS - BVSS| (Note 2) GND2 Input Current, Any Pin Except Supplies IIN Analog Input Voltage VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature (powered applied) Ta -10 Storage Temperature Tstg -65
Note 1. All voltages with respect to ground. Note 2. AVSS, DVSS and BVSS must be connected to the same analog ground plane.
max 4.6 4.6 4.6 0.3 0.3 10 AVDD+0.3 DVDD+0.3 70 150
Units V V V V V mA V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, BVSS=0V; Note 1) Parameter Symbol min typ Power Supplies Analog AVDD 2.6 3.3 (Note 3) Digital DVDD 2.6 3.3 16bit Mono CODEC BVDD 2.6 3.3 Differences 0 AVDD-BVDD -0.1 0 AVDD-DVDD -0.3 0 BVDD-DVDD -0.3
Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD, DVDD and BVDD is not critical.
max 3.6 3.6 3.6 +0.1 +0.3 +0.3
Units V V V V V V
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0301-E-00 -5-
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ASAHI KASEI
[AK4641]
ANALOG CHARACTERISTICS (Ta=25C; AVDD=DVDD=BVDD=3.3V; AVSS=DVSS=BVSS=0V; Signal Frequency=1kHz; 16bit Data; Stereo CODEC: fs=44.1kHz, BICK=64fs; Measurement frequency=20Hz 20kHz; Mono CODEC: Bfs=8kHz; BBICK=32Bfs; Measurement frequency=20Hz 3.4kHz; unless otherwise specified) Min typ max Units Parameter MIC Amplifier Input Resistance 20 30 40 k MGAIN bit = "0" 0 dB Gain MGAIN bit = "1" +20 dB MIC Power Supply Output Voltage (Note 4) 2.22 2.47 2.72 V Load Resistance 2 k Load Capacitance 30 pF MIC Detection Comparator Voltage Level (Note 5) 0.165 0.257 V Internal pull down Resistance 250 500 750 k Input PGA Characteristics: Input Resistance (Note 6) 5 10 15 k Step Size 0.1 0.5 0.9 dB Max (IPGA6-0 bits = "47H") +27.5 dB Gain Control Range Min (IPGA6-0 bits = "00H") dB -8 ADC Analog Input Characteristics of Stereo CODEC: MIC Gain=+20dB, IPGA=0dB, ALC1=OFF, MIC IPGA ADC of Stereo CODEC Resolution 16 Bits Input Voltage (MIC Gain=+20dB, Note 7) 0.168 0.198 0.228 Vpp S/(N+D) 71 81 dB (-1dBFS) D-Range 78 86 dB (-60dBFS, A-weighted) MIC Gain=+20dB, A-weighted 78 86 dB S/N MIC Gain=0dB, A-weighted 92 dB DAC Characteristics of Stereo CODEC: Resolution 16 Bits Stereo Line Output Characteristics: RL=10k, DAC of Stereo CODEC LOUT/ROUT pins Output Voltage (Note 8) 1.78 1.98 2.18 Vpp S/(N+D) (0dBFS) 76 86 dBFS S/N (A-weighted) 82 90 dB Interchannel Isolation 100 dB Interchannel Gain Mismatch 0.1 0.5 dB Load Resistance 10 k Load Capacitance 30 pF
Note 4. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ). Note 5. Comparator Voltage Level is proportional to AVDD voltage. Vout = 0.05 x AVDD (min), 0.078 x AVDD (max). Note 6. When IPGA Gain is changed, this typical value changes between 8k and 11k. Note 7. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ). Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
MS0301-E-00 -6-
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ASAHI KASEI
[AK4641]
Min Typ max Units Parameter Mono Line Output Characteristics: RL=20k, DAC of Stereo CODEC MOUT+/MOUT- pins Output Voltage 0.305 Vpp MOGN bit = "1", -17dB (Note 9) MOGN bit = "0", +6dB 3.56 3.96 4.36 Vpp 74 dBFS MOGN bit = "1", -17dB S/(N+D) (0dBFS) MOGN bit = "0", +6dB 76 86 dBFS 77 dB MOGN bit = "1", -17dB S/N (A-weighted) MOGN bit = "0", +6dB 83 93 dB 2 MOGN bit = "1", -17dB k Load Resistance MOGN bit = "0", +6dB 20 k Load Capacitance 30 pF AUX Input: AUXIN+, AUXIN- pins: AUXSI bit = "0" Maximum Input Voltage (Note 10) 1.98 Vpp Input Resistance 25 40 55 k Step Size 1 3 5 dB Max (GN3-0 bits = "FH") +24 dB Gain Control Range Min (GN3-0 bits = "0H") dB -21 Mono Output: RL=10k, DAC of Stereo CODEC MIX MOUT2 pin Output Voltage (Note 11) 1.78 1.98 2.18 Vpp S/(N+D) (0dBFS) 76 86 dB S/N (A-weighted) 83 93 dB Load Resistance 10 k Load Capacitance (Note 12) 30 pF 16bit Mono ADC Analog Input Characteristics: AUXIN pin MIX ADC of Mono CODEC: AUX Volume = 0dB Resolution 16 Bits Input Voltage (Note 13) 1.68 1.98 2.28 Vpp S/(N+D) 65 75 dB (-1dBFS) S/N 79 89 dB 16bit Mono DAC Analog Output Characteristics: DAC of Mono CODEC MOUT+/- pins: MOGN = +6dB Resolution 16 Bits Output Voltage (Note 14) 3.56 3.96 4.36 Vpp S/(N+D) 68 78 dB S/N 82 92 dB Power Supplies Power Up (PDN pin = "H") AVDD+DVDD+ BVDD 17 27 mA Power Down (PDN pin = "L") (Note 15) AVDD+DVDD+BVDD 100 A Note 9. Output voltage is proportional to AVDD voltage. Vout = 1.2 x AVDD (typ) @MOGN bit = "0", 0.092 x AVDD (typ) @MOGN bit = "1" at differential Output. Note 10. Maximum Input Voltage is proportional to AVDD voltage. Vin = (AUXIN+) - (AUXIN-) = 0.6 x AVDD (typ) at AUXSI bit = "0", Vin = AUXIN+ = 0.6 x AVDD (typ) at AUXSI bit = "1". Note 11. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ). Note 12. When the output pin drives a capacitive load, a resistor should be added in series between the output pin and capacitive load. Note 13. Input voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD (typ). Note 14. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ). Note 15. All digital input pins are fixed to DVSS. When the voltage difference among DVDD, BVDD and AVDD is larger than 0.3V, the power supply current at power down mode increases.
MS0301-E-00 -7-
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ASAHI KASEI
[AK4641]
FILTER CHARACTERISTICS (Stereo CODEC) (Ta=-10 70C; AVDD, DVDD, BVDD=2.6 3.6V; fs=44.1kHz; DEM=OFF) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 16) PB 0 0.1dB 20.0 -1.0dB 21.1 -3.0dB Stopband SB 25.7 Passband Ripple PR Stopband Attenuation SA 68 Group Delay (Note 17) GD 17.0 Group Delay Distortion 0 GD ADC Digital Filter (HPF): Frequency Response FR 3.4 -3.0dB (Note 16) 10 -0.5dB 22 -0.1dB DAC Digital Filter: Passband (Note 16) PB 0 0.1dB 20.0 -0.7dB 22.05 -6.0dB Stopband SB 25.2 Passband Ripple PR Stopband Attenuation SA 59 Group Delay (Note 17) GD 17.9 DAC Digital Filter + SCF: FR Frequency Response: 0 20.0kHz 1.0
max 17.4 0.1 19.6 0.01 -
Units kHz kHz kHz kHz dB dB 1/fs s Hz Hz Hz kHz kHz kHz dB dB 1/fs dB
Note 16. The passband and stopband frequencies scale with fs (system sampling rate). For example, ADC is PB=0.454*fs (@-1.0dB), DAC is PB=0.454*fs (@-0.01dB). Note 17. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16bit data of both channels from the input register to the output of analog signal.
MS0301-E-00 -8-
2004/05
ASAHI KASEI
[AK4641]
FILTER CHARACTERISTICS (16bit Mono CODEC) (Ta=-10 70C; AVDD, DVDD, BVDD=2.6 3.6V; Bfs=8kHz) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 16) PB 0 0.1dB 3.6 -1.0dB 3.8 -3.0dB Stopband SB 4.7 Passband Ripple PR Stopband Attenuation SA 68 Group Delay (Note 17) GD 17.0 Group Delay Distortion 0 GD ADC Digital Filter (HPF): Frequency Response FR 0.62 -3.0dB (Note 16) 1.81 -0.5dB 3.99 -0.1dB DAC Digital Filter: Passband (Note 16) PB 0 0.1dB 3.6 -0.7dB 4.0 -6.0dB Stopband SB 4.6 Passband Ripple PR Stopband Attenuation SA 59 Group Delay (Note 17) GD 15.8 DAC Digital Filter + SCF: FR Frequency Response: 0 20.0kHz 1.0
max 3.1 0.1 3.6 0.01 -
Units kHz kHz kHz kHz dB dB 1/Bfs s Hz Hz Hz kHz kHz kHz dB dB 1/Bfs dB
Note 16. The passband and stopband frequencies scale with fs (system sampling rate). For example, ADC is PB=0.454*Bfs (@-1.0dB), DAC is PB=0.454*Bfs (@-0.01dB). Note 17. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16bit data of both channels from the input register to the output of analog signal.
MS0301-E-00 -9-
2004/05
ASAHI KASEI
[AK4641]
DC CHARACTERISTICS (Ta=-10 70C; AVDD, DVDD, BVDD=2.6 3.6V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL Input Voltage at AC Coupling (Note 18) VAC 50%DVDD High-Level Output Voltage VOH (Iout=-200A) DVDD-0.2 Low-Level Output Voltage VOL (Except SDA pin: Iout=200A) (SDA pin: Iout=3mA) VOL Input Leakage Current Iin Note 18. The external clock is input to MCLK pin via AC coupled capacitor.
typ -
Max 30%DVDD 0.2 0.4 10
Units V V V V V V A
SWITCHING CHARACTERISTICS (Ta=-10 70C; AVDD, DVDD, BVDD=2.6 3.6V; CL=20pF) Parameter Symbol min 16bit Stereo CODEC Interface Timing: Master Clock Timing (MCLK pin) Frequency fCLK 1.792 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK AC Pulse Width (Note 19) tACW 0.4/fCLK LRCK Timing Frequency fs 7 Duty Cycle Duty 45 Audio Interface Timing BICK Period tBCK 312.5 BICK Pulse Width Low tBCKL 130 Pulse Width High tBCKH 130 LRCK Edge to BICK "" (Note 20) tLRB 50 BICK "" to LRCK Edge (Note 20) tBLR 50 LRCK to SDTO (MSB) (Except I2S mode) tLRS BICK "" to SDTO tBSD SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50
Note 19. Refer to Figure 3. Note 20. BICK rising edge must not occur at the same time as LRCK edge.
typ
max
Units
-
12.288 48 55 80 80 -
MHz ns ns ns kHz % ns ns ns ns ns ns ns ns ns
MS0301-E-00 - 10 -
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ASAHI KASEI
[AK4641]
Parameter 16bit Mono CODEC Interface Timing: SYNC Timing Frequency (PLL Lock Range) Serial Interface Timing at Short/long Frame Sync BBICK Frequency BBICK Period BBICK duty cycle BBICK Pulse Width Low Pulse Width High BSYNC Edge to BBICK " " BBICK " " to BSYNC Edge BSYNC to BSDTO (MSB) (Except Short Frame) BBICK " " to BSDTO BSDTI Hold Time BSDTI Setup Time BSYNC Pulse Width Low Pulse Width High Serial Interface Timing at MSB justified and I2S BBICK Frequency BBICK Period BBICK duty cycle BBICK Pulse Width Low Pulse Width High BSYNC Edge to BBICK " " BBICK " " to BSYNC Edge BSYNC to BSDTO (MSB) (Except I2S mode) BBICK " " to BSDTO BSDTI Hold Time BSDTI Setup Time BSYNC Duty Cycle Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 21) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Reset Timing PDN Pulse Width (Note 22) PMADC "" to SDTO valid (Note 23) PMAD2 "" to BSDTO valid (Note 24)
Symbol
min
typ
max
Units
Bfs fBBCK tBBCK tBDUT tBBCKL tBBCKH tBSYB tBBSY tBSYD tBBSD tBSDH tBSDS tBBSL tBBSH fBBCK tBBCK tBDUT tBBCKL tBBCKH tBSYB2 tBBSY2 tBSYD2 tBBSD2 tBSDH2 tBSDH2 BDuty2 fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF TSU:STO tSP tPD tPDV tBPDV
8 128 488
-
16 2048
kHz kHz ns % ns ns ns ns ns ns ns ns ns ns kHz ns % ns ns ns ns ns ns ns ns % kHz s s s s s s s s s s ns ns 1/fs 1/Bfs
50 200 200 50 50 80 80 50 50 3300 440 256 488 50 200 200 50 50 80 80 50 50 45 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0 150 2081 1057 50 55 400 0.3 0.3 50 2048
Note 21. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 22. The AK4641 can be reset by the PDN pin = "L". Note 23. This is the count of LRCK "" from the PMADC bit = "1". Note 24. This is the count of BSYNC "" from the PMAD2 bit = "1". Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips.
MS0301-E-00 - 11 -
2004/05
ASAHI KASEI
[AK4641]
Timing Diagram
1/fCLK VIH MCLK VIL tCLKH 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL tCLKL
Figure 2. Clock Timing of Stereo CODEC
1/fCLK
1000pF MCLK Input 100k DVSS Monitoring Point DVSS
tACW
tACW
VAC
Note. This circuit shows how to monitor MCLK AC Coupling Timing. This circuit is not used in actual system. Figure 3. MCLK AC Coupling Timing
MS0301-E-00 - 12 -
2004/05
ASAHI KASEI
[AK4641]
VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD
SDTO tSDS tSDH
50%DVDD
VIH SDTI VIL
Figure 4. Audio Interface Timing of Stereo CODEC
1/Bfs VIH BSYNC VIL tBBSL tBBSH
tBBC K VIH BBIC K tBBC KH tBBC KL VIL
Figure 5. Clock Timing of 16bit Mono CODEC
MS0301-E-00 - 13 -
2004/05
ASAHI KASEI
[AK4641]
BSYNC tBBSY tBSYB
VIH VIL
BBICK tBSYD
VIH VIL tBBSD
BSDTO tBSDS tBSDH
50%DVDD
BSDTI
VIH VIL
Figure 6. 16bit Mono CODEC Interface Timing at short and long frame sync
BSYNC tBBSY2 tBSYB2
VIH VIL
BBICK tBSYD2
VIH VIL tBBSD2
BSDTO tBSDS2 tBSDH2
50%DVDD
BSDTI
VIH VIL
Figure 7. 16bit Mono CODEC Interface Timing at MSB justified and I2S
MS0301-E-00 - 14 -
2004/05
ASAHI KASEI
[AK4641]
SDA
tBUF tLOW tR tHIGH tF tSP
VIH VIL
VIH SCL VIL
tHD:STA Stop Start
2
tHD:DAT
tSU:DAT
tSU:STA Start
tSU:STO Stop
Figure 8. I C Bus Mode Timing
PMADC bit tPDV
SDTO
50%DVDD
Figure 9. Power Down & Reset Timing 1
PMAD2 bit tBPDV
BSDTO
50%DVDD
Figure 10. Power Down & Reset Timing 2
tPD PDN VIL
Figure 11. Power Down & Reset Timing 3
MS0301-E-00 - 15 -
2004/05
ASAHI KASEI
[AK4641]
OPERATION OVERVIEW System Clock Input
The AK4641 requires a master clock (MCLK). This master clock is input to the AK4641 by inputting an external CMOS-level clock to the MCLK pin or by inputting an external clock that is greater than 50% of the DVDD level to the MCLK pin through a capacitor. MCKPD and MCKAC bits should be set as shown in Table 1. ADC and DAC of 16bit Stereo CODEC are powered-down at MCKPD bit = "1". Status MCKAC bit Clock is input to MCLK pin. 0 Clock is not input to MCLK pin. 0 AC Coupling Input (Figure 13) Clock is input to MCLK pin. 1 Clock is not input to MCLK pin. 1 Table 1. MCKPD and MCKAC bits Setting for Master Clock Status Master Clock External Clock Direct Input (Figure 12) MCKPD bit 0 1 0 1
(1) External Clock Direct Input
MCLK
External Clock
MCKAC bit = "0" MCKPD bit = "0"
AK4641
Figure 12. External Master Clock Input Block
(2) AC Coupling Input
0.1uF External Clock
MCLK
MCKAC bit = "1" MCKPD bit = "0"
AK4641
Figure 13. External Clock mode (Input: 50%DVDD)
MS0301-E-00 - 16 -
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ASAHI KASEI
[AK4641]
The clock required to operate are MCLK, LRCK (fs) and BICK ( 32fs). Then the master clock (MCLK) should be synchronized with LRCK. The phase between these clocks does not matter. The S/N of the DAC of Stereo CODEC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output of Stereo CODEC through Headphone amp at fs=8kHz is shown in Table 3. MCK1 0 0 1 1 MCK0 0 1 0 1 Sampling Frequency MCLK (fs) 256fs 7kHz48kHz 512fs 7kHz24kHz 1024fs 7kHz12kHz N/A Table 2. Select Master Clock Frequency
Default
MCLK S/N (fs=8kHz, A-weighted) 256fs 82dB 512fs 90dB 1024fs 90dB Table 3. Relationship between MCLK and S/N of Line Out When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4641 may occur pop noise. All external clocks (MCLK, BICK and LRCK) should always be present when either ADC or DAC of Stereo CODEC is power-up. If these clocks are not provided, the AK4641 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4641 should be in the power-down mode.
BICK pin LRCK pin
Power up Power down Input Fixed to "L" or "H" externally Input Fixed to "L" or "H" externally Table 4. Clock Operation
System Reset
Upon power-up, reset the AK4641 by bringing the PDN pin = "L". This ensures that all internal registers are reset to their initial values. The ADC of Stereo CODEC enters an initialization cycle that starts when the PMADC bit is changed from "0" to "1". The initialization cycle time is 2081/fs, or 47.2ms@fs=44.1kHz. During the initialization cycle, the ADC digital data output of Stereo CODEC is forced to a 2's compliment, "0". The ADC output of Stereo CODEC reflects the analog input signal after the initialization cycle is complete. The DAC of Stereo CODEC does not require an initialization cycle. The ADC of Mono CODEC enters an initialization cycle that starts when the PMAD2 bit is changed from "0" to "1". The initialization cycle time is 1057/Bfs, or 132ms@Bfs=8kHz. During the initialization cycle, the ADC digital data output of Mono CODEC is forced to a 2's compliment, "0". The ADC output of Mono CODEC reflects the analog input signal after the initialization cycle is complete. The DAC of Mono CODEC does not require an initialization cycle.
MS0301-E-00 - 17 -
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ASAHI KASEI
[AK4641]
Audio Interface Format of Stereo CODEC
Three types of data formats are available and are selected by setting the DIF1-0 bits. In all modes, the serial data is MSB first, 2's complement format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge. LRCK and BICK must be input to the AK4641 in slave mode. If 16bit data that ADC of Stereo CODEC outputs is converted to 8bit data by removing LSB 8bit, "-1" at 16bit data is converted to "-1" at 8bit data. And when the DAC of Stereo CODEC playbacks this 8bit data, "-1" at 8bit data will be converted to "-256" at 16bit data and this is a large offset. This offset can be removed by adding the offset of "128" to 16bit data before converting to 8bit data. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 SDTO (ADC) SDTI (DAC) BICK 0 MSB justified LSB justified 32fs 1 MSB justified MSB justified 32fs 0 I2S I2S 32fs 1 N/A N/A N/A Table 5. Audio Interface Format of Stereo CODEC Figure Figure 14 Figure 15 Figure 16 -
Default
LRCK
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i)
15 14 13 Don't Care 15:MSB, 0:LSB Lch Data Rch Data 10 15 14 10 Don't Care 15 14 210 15 15 14 13 15 14 13 0123 76543210 7 6 5 4 3 2 1 0 15 14 13 15 16 17 18 31 0 1 2 3 15 7 6 5 4 3 2 1 0 15 15 16 17 18 31 0 1
Figure 14. Mode 0 Timing
MS0301-E-00 - 18 -
2004/05
ASAHI KASEI
[AK4641]
LRCK
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i)
15 14 13 15 14 13 15:MSB, 0:LSB Lch Data Rch Data 10 10 Don't Care 15 14 13 10 Don't Care 15 15 15 14 13 15 14 13 0123 76543210 7 6 5 4 3 2 1 0 15 14 13 15 16 17 18 31 0 1 2 3 15 7 6 5 4 3 2 1 0 15 15 16 17 18 31 0 1
Figure 15. Mode 1 Timing
LRCK
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i)
15 14 15 14 210 210 Don't Care 15 14 210 Don't Care 15 14 0 15 14 0123 876543210 8 7 6 5 4 3 2 1 0 15 14 15 16 17 18 31 0 1 2 3 876543210 15 16 17 18 31 0 1
15:MSB, 0:LSB Lch Data Rch Data
Figure 16. Mode 2 Timing
MS0301-E-00 - 19 -
2004/05
ASAHI KASEI
[AK4641]
Audio Interface Format of Mono CODEC
Four types of data formats are available for 16bit Mono CODEC and are selected by setting the BTFMT1-0 bits. In all modes, the serial data is MSB first, 2's complement format. In short frame sync and long frame sync modes, the BSDTO is clocked out on the rising edge of BBICK and the BSDTI is latched on the falling edge. In MSB justified and I2S modes, the BSDTO is clocked out on the falling edge of BBICK and the BSDTI is latched on the rising edge. BSYNC and BBICK must be input to the AK4641.
Mode BTFMT1-0 BBICK Figure Short Frame Sync 00 Figure 17 Default 16Bfs Long Frame Sync 01 Figure 18 16Bfs MSB justified 10 Figure 19 32Bfs I 2S 11 Figure 20 32Bfs Table 6. Audio Interface Format for 16bit Mono CODEC (1) Short Frame Sync
1/Bfs
BSYNC
BBICK
BSDTO
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
BSDTI
Don't Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 Don't Care
D15 D14
Figure 17. Timing of Short Frame Sync
(2) Long Frame Sync
1/Bfs
BSYNC
BBICK
BSDTO
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
BSDTI
Don't Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 Don't Care
D15 D14 D13
Figure 18. Timing of Long Frame Sync
MS0301-E-00 - 20 -
2004/05
ASAHI KASEI
[AK4641]
(3) MSB justified
BSYNC
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BBICK (32Bfs) BSDTO(o) BSDTI(i) BBICK (64Bfs) BSDTO(o) BSDTI(i)
15 14 13 15 14 13 0123
76543210 76543210 15 16 17 18 Don't Care Don't Care 15 16 17 18
15 15 31 0 1
31 0 1 2 3
15 14 13 15 14 13 15:MSB, 0:LSB
10 10 Don't Care Don't Care
15 15
Figure 19. Timing of MSB justified (4) I2S
BSYNC BBICK (32Bfs) BSDTO(o) BSDTI(i) BBICK (64Bfs) BSDTO(o) BSDTI(i)
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
15 14 15 14 0123
876543210 876543210 15 16 17 18 31 0 1 2 3 Don't Care 15 16 17 18 31 0 1
15 14 15 14
210 210 Don't Care Don't Care
15:MSB, 0:LSB
Figure 20. Timing of I2S
Digital High Pass Filter
The ADC of Stereo CODEC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 3.4Hz (@fs=44.1kHz) and scales with sampling rate (fs). The ADC of Mono CODEC also has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.62Hz (@Bfs=8kHz) and scales with sampling rate (Bfs).
MS0301-E-00 - 21 -
2004/05
ASAHI KASEI
[AK4641]
MIC Input
MICL bit
ATT
Stereo Mixer MICM bit Mono Mixer
ADC of Stereo CODEC
DAC of Mono CODEC
ATT
IPGA with ALC Mic In 0dB/+20dB
MICAD bit
P
AUXAD bit DAC2 bit = "0": Mic Input Signal "1": DAC Signal AUX IN
Figure 21. Microphone Input The AK4641 has the following functions for Mic Input. (1) 1st MIC Amplifier of 20dB gain that can be selected ON/OFF by "MGAIN" bit. (2) 2nd Amplifier that has PGA with ALC. This volume is controlled by "IPGA6-0" bit as Table 7. While ALC is working, Master Clock must be present. When Master Clock is not provided or PMMIC bit = "0", it is invalid to write to "IPGA6-0". (3) Attenuator for stereo mixer. This volume is controlled by "ATTS2-0" bit as Table 8. (4) Attenuator for mono mixer. This attenuator level is 4dB and this ON/OFF is controlled by "ATTM" bit. IPGA6-0 GAIN (dB) STEP 47H +27.5 46H +27.0 45H +26.5 : : 36H +19.0 : : 10H +0.0 Default : : 0.5dB 06H -5.0 05H -5.5 04H -6.0 03H -6.5 02H -7.0 01H -7.5 00H -8.0 Table 7. Microphone Input Gain Setting ATTS2-0 7H 6H 5H 4H 3H 2H 1H 0H Attenuation -6dB -9dB Default -12dB -15dB -18dB -21dB -24dB -27dB Table 8. Attenuator Table
MS0301-E-00 - 22 -
2004/05
ASAHI KASEI
[AK4641]
MIC Gain Amplifier
The AK4641 has a Gain Amplifier for Microphone input. This gain is 0dB or +20dB, selected by the MGAIN bit. The typical input impedance is 30k. MGAIN bit Input Gain 0 0dB 1 +20dB Table 9. Input Gain
Default
MIC Power
The MPI and MPE pins supply power for the Microphone. These output voltages are 0.75 x AVDD (typ) and the load resistance is 2k(min). No capacitor must be connected directly to MPI and MPE pins. MPWRI/MPWRE bit can control output from MPI and MPE pin.
MPWRE bit
MPE
AK4641
MPI INT EXT
MPWRI bit
Headset
G
M
R
L
MDT DTMIC bit
or
Headphone G R L
500k
0.075 x AVDD
Figure 22. Microphone Power Supply and Mic Detection
MIC Detection Function
The AK4641 includes the detection function of microphone. The external circuit is showed in Figure 22. The followings show the example of external microphone detection sequence: (1) MPWRE bit = "1". (2) MPE drives external microphone. (3) DTMIC bit is set as Table 10. In case of Headset, the input voltage of MDT pin is higher than 0.078 x AVDD because of the relationship between the bias resistance at MPE pin (typ. 2.2k) and the microphone impedance. In case of Headphone, the input voltage of MDT pin is 0V because the pin of headphone jack connected to MDT pin is assigned as ground. Input Level of DTM DTMIC Result 1 Mic (Headset) 0.078 x AVDD < 0.050 x AVDD 0 No Mic (Headphone) Table 10. Microphone Detection Result
MS0301-E-00 - 23 -
2004/05
ASAHI KASEI
[AK4641]
Manual Mode
The AK4641 becomes a manual mode at ALC1 bit = "0". This mode is used in the case shown below. 1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc) 2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed. For example; When the change of the sampling frequency. 3. When IPGA is used as a manual volume.
MIC-ALC Operation
The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is "1". [1] ALC1 Limiter Operation When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH), the IPGA value is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically. When the ZELM bit = "1", the timeout period is set by the LTM1-0 bits. The operation for attenuation is done continuously until the input signal level becomes LMTH or less. If the ALC1 bit does not change into "0" after completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds LMTH. When the ZELM bit = "0", the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation function so that the IPGA value is attenuated at the zero-detect points of the waveform. [2] ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4641 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation. If the input signal does not exceed the "ALC1 Recovery Waiting Counter Reset Level", the ALC1 recovery operation starts. The IPGA value increases automatically during this operation up to the reference level (REF6-0 bits). The ALC1 recovery operation is done at a period set by the WTM1-0 bits. Zero crossing is detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next recovery operation starts. During the ALC1 recovery operation, when input signal level exceeds the ALC1 limiter detection level (LMTH), the ALC1 recovery operation changes immediately into an ALC1 limiter operation. In the case of "(Recovery waiting counter reset level) IPGA Output Level < Limiter detection level" during the ALC1 recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of "(Recovery waiting counter reset level) > IPGA Output Level", the wait timer for the ALC1 recovery operation starts. The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation becomes faster than a normal recovery operation.
MS0301-E-00 - 24 -
2004/05
ASAHI KASEI
[AK4641]
[3] Example of ALC1 Operation Table 11 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB. Register Name LMTH LTM1-0 ZELM ZTM1-0 WTM1-0 REF6-0 IPGA6-0 LMAT1-0 RATT ALC1 Comment fs=8kHz Operation -4dBFS Don't use Enable 16ms fs=16kHz Data Operation 1 -4dBFS 00 Don't use 0 Enable 01 16ms 16ms +27.5dB 0dB 1 step 1 step Enable fs=44.1kHz Data Operation 1 -4dBFS 00 Don't use 0 Enable 10 11.6ms 10 47H 10H 00 0 1 11.6ms +27.5dB 0dB 1 step 1 step Enable
Limiter detection Level Limiter operation period at ZELM = 1 Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same data 00 16ms 01 as ZTM1-0 bits Maximum gain at recovery operation 47H +27.5dB 47H Gain of IPGA at ALC1 operation Start 10H 0dB 10H Limiter ATT Step 00 1 step 00 Recovery GAIN Step 0 1 step 0 ALC1 Enable bit 1 Enable 1 Table 11. Example of the ALC1 setting
Data 1 00 0 00
The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1 operation is finished by ALC1 bit = "0" or PMMIC bit = "0".
* LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
IPGA gain at ALC1 operation start can be changed from the default value of IPGA6-0 bits while PMMIC bit is "1" and ALC1 bit is "0". When ALC1 bit is changed from "1" to "0", IPGA holds the last gain value set by ALC1 operation.
Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms @ fs= 8kHz Limiter and Recovery Step = 1 Maximum Gain = +27.5dB Manual Mode Limiter Detection Level = -4dBFS (1) Addr=08H, Data=00H
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (REF6-0)
(2) Addr=0AH, Data=47H
WR (IPGA6-0)
* The value of IPGA should be the same or smaller than REF's
(3) Addr=0BH, Data=10H
WR (ALC1= "1", LMAT1-0, RATT, LMTH, ZELM)
(4) Addr=09H, Data=21H
* ALC1 bit must be set to "1" at more than zero cross time out period ALC1 Operation after the value of IPGA is set (see figure 22).
Note : WR : Write Figure 23. Registers set-up sequence at ALC1 operation
MS0301-E-00 - 25 -
2004/05
ASAHI KASEI
[AK4641]
[Setting timing of IPGA and ALC1 bits]
t > zero cross time out period
ZTM1-0 bits
XXH AH AH
00H BH
XXH
IPGA6-0 bits
IPGA ALC1 bit
BH
(1) (2)
(3) (4)
(5)
Figure 24. Setting timing of IPGA and ALC1 bits (1) (2) (3) (4) (5) Set the zero cross time out period of IPGA as 128/fs: ZTM1-0 bits = "00". (Note) Set the IPGA value of ALC1 operation start by IPGA6-0 bits. The value of IPGA6-0 bits is reflected to actual gain at zero crossing or zero cross time out. Set the zero cross time out period of ALC1 operation by ZTM1-0 bits after the zero cross time out period set by (1). Set ALC1 bit to "1".
(Note) If ZTM1-0 bits are set to the value except for "00", ALC1 bit must be set to "1" after this zero cross time out period.
MS0301-E-00 - 26 -
2004/05
ASAHI KASEI
[AK4641]
DAC of Stereo CODEC
DACL bit Stereo Mixer
DEM SMUTE
5 Band Equalizer
DATT
DAC of Stereo CODEC
Mono Mixer DACM bit
Figure 25. DAC block diagram of Stereo CODEC The AK4641 has the following functions for DAC of Stereo CODEC. (1) 5 Band Equalizer (2) Soft mute (3) Digital Attenuator (4) De-emphasis Filter (32kHz, 44.1kHz and 48kHz)
De-emphasis Filter
The AK4641 includes the digital de-emphasis filter (tc = 50/15s) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter. DEM1 0 0 1 1 DEM0 Mode 0 44.1kHz 1 OFF Default 0 48kHz 1 32kHz Table 12. De-emphasis Control
Digital Attenuator
The AK4641 has a channel-independent digital attenuator (256levels, 0.5dB step, Mute). The ATTL/R7-0 bits set the attenuation level of each channel (Table 13). When the DATTC bit = "1", the ATTL7-0 bits control both Lch and Rch attenuation levels. When the DATTC bit = "0", the ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level. This attenuator has a soft transition function. It takes around 1061/fs (24ms@44.1kHz) at TM bit = "0" and 256/fs (5.8ms@44.1kHz) at TM bit = "1" from 00H to FFH. ATTL/R7-0 Attenuation 00H 0dB Default 01H -0.5dB 02H -1.0dB 03H -1.5dB : : : : FDH -126.5dB FEH -127.0dB FFH MUTE (-) Table 13. DATT Code Table
MS0301-E-00 - 27 -
2004/05
ASAHI KASEI
[AK4641]
5 Band Equalizer
The AK4641 has 5 Band Equalizer before DAC of Stereo CODEC as shown in Figure 25. The center frequencies and cut/boost amount are the followings.
* Center frequency: 100Hz, 250Hz, 1kHz, 3.5kHz, 10kHz (Note 25, Note 26) * Cut/Boost amount: Minimum -10.5dB, Maximum +12dB, Step 1.5dB
Note 25: These are the frequencies when the sampling frequency is 44.1kHz. These frequencies are proportional to the sampling frequency. Note 26: 100Hz is not center frequency but the frequency component lower than 100Hz is controlled. Note 27: 10kHz is not center frequency but the frequency component higher than 10kHz is controlled. EQ5 bit controls ON/OFF of this Equalizer and these Boost amount are set by EQx3-0 bit as shown in Table 14. EQA3-0: EQB3-0: EQC3-0: EQD3-0: EQE3-0: Select the boost level of 100Hz Select the boost level of 250Hz Select the boost level of 1kHz Select the boost level of 3.5kHz Select the boost level of 10kHz EQx3-0 Boost amount 0H +12.0dB 1H +10.5dB 2H +9.0dB 3H +7.5dB : : 8H 0dB Default : : DH -7.5dB EH -9.0dB FH -10.5dB Table 14. Boost amount of 5 Band Equalizer
MS0301-E-00 - 28 -
2004/05
ASAHI KASEI
[AK4641]
Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit goes to "1", the output signal is attenuated by - ("0") during the cycle set by the TM bit. When the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to the digital attenuator level of ATTL/R7-0 bits during the cycle set by the TM bit. If the soft mute is cancelled within the cycle set by the TM bit after starting the operation, the attenuation is discontinued and returned to the digital attenuator level. The soft mute is effective for changing the signal source without stopping the signal transmission. Table 15 shows the Soft Mute Time when the digital attenuator level is 0dB (ATTL/R7-0 bits = "0"). As the digital attenuator level is less than 0dB, the Soft Mute Time becomes shorter. TM Cycle 0 1061/fs Default 1 256/fs Table 15. Soft Mute Time Setting
S M U TE bit
T M bit T M bit
A TTL/R 7-0 bits A ttenuation
(1) (3)
-
GD (2) A nalog O utput GD
Figure 26. Soft Mute Function
NOTE: (1) The output signal is attenuated until - ("0") by the cycle set by the TM bit. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle of setting the TM bit, the attenuation is discounted and returned to 0dB(the set value).
MS0301-E-00 - 29 -
2004/05
ASAHI KASEI
[AK4641]
AUX Input
GN3-0 bits AUXIN+ AUXIN- Volume AUXAD bit
AUXL bit Stereo Mixer Mixer for ADC of Stereo CODEC
Figure 27. AUX Input AUX input is differential input at AUXSI bit = "0" and single end input at AUXSI bit = "1". AUXIN+ pin should be used at single end input (AUXSI bit = "1"). The AK4641 has a volume for AUX Input. This Volume is controlled by GN3-0 bits as shown in Table 16. The switching noise occurs when GN3-0 bits are changed. GN3-0 GAIN (dB) FH +24.0 EH +21.0 DH +18.0 : : 7H +0.0 Default : : 2H -15.0 1H -18.0 0H -21.0 Table 16. AUX Input Gain Setting
MS0301-E-00 - 30 -
2004/05
ASAHI KASEI
[AK4641]
STEREO LINE OUTPUT (LOUT and ROUT pins) and MONO LINE OUTPUT (MOUT2 pin)
DAC of Mono CODEC DAC2 bit Mic In 0dB/+20dB IPGA DACL bit
ATT + DAC of Stereo CODEC ATT
MICL bit Stereo Line Out
External Headphone Amp
AUXL bit AUX In Mono Line Out(MOUT2) Volume External Speaker Amp
Figure 28. Stereo Line Output and Mono Line Out2 Line out path does not have volume but the attenuator of DAC of Stereo CODEC, volume of Mic In and AUX In control the output signal level. The AK4641 does not have mute circuits to remove pop noise at power up and down for Line Output. The signal of the stereo mixer is converted to a mono signal [(L+R)/2] and this signal is output via MOUT2 pin.
MONO LINE OUTPUT (MOUT+/MOUT- pin)
DAC of Mono CODEC DAC2 bit ATT MIC In 0dB/+20dB IPGA MICM bit DACM bit MOGN bit
ATT + DAC of Stereo CODEC
1/2 1/2 -17dB/+6dB
MOUT+ MOUT-
Figure 29. Mono Output Mono mixer mixes signal from MIC In, Lch signal and Rch signal from DAC of Stereo CODEC. This mixed signal is output from the MOUT+ and MOUT- pins by differential output. Amp for mono output has 6dB gain and -17dB gain that are set by the MOGN bit.
MS0301-E-00 - 31 -
2004/05
ASAHI KASEI
[AK4641]
16bit Mono CODEC for Bluetooth I/F
The AK4641 has the 16bit Mono CODEC to connect with Bluetooth Module that supports 8kHz to 16kHz sample rate. The AK4641 includes PLL that generate the master clock for Mono CODEC from input BSYNC signal. The PLL should be powered-up after BSYNC signal is inputted. The PLL needs 90ms (max) lock time, when the PLL is powered-up (PMBIF bit = "0" "1") and BSYNC is input. PMDA2 bit should be set to "0" or "0" data should be input to DAC of Mono CODEC during 90ms after PMBIF bit is set to "1". BBICK and BSYNC should always be present when either ADC or DAC of Mono CODEC is power-up. If these clocks are not provided, the AK4641 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If BBICK or BSYNC is not present, ADC and DAC of Mono CODEC should be in the power-down mode. ADC The ADC of Mono CODEC outputs the signal from DAC of Stereo CODEC, Mic In and AUX In. The ADC of Mono CODEC enters an initialization cycle that starts when the PMAD2 bit is changed from "0" to "1". The initialization cycle time is 1057/Bfs, or 132ms@Bfs=8kHz. During the initialization cycle, the ADC digital data output of Mono CODEC are forced to a 2's compliment, "0". The ADC output of Mono CODEC reflects the analog input signal after the initialization cycle is complete.
* ADC full Scale Level: 0.6*AVDD [Vpp](1.98Vpp@3.3V) Full Scale level of ADC of Mono CODEC is the same as that of DAC of Stereo CODEC.
DAC of Mono CODEC DAC2 bit ATT Mic In 0dB/+20dB IPGA MICL bit DACL bit
ATT + Stereo DAC
AK4641
ADC2 bit
ADC of Mono CODEC Bluetooth Module
Bth Headset
AUXL bit AUX In Volume
Line Out
External HP-Amp
Headphone
Figure 30. Path to ADC of Mono CODEC DAC The signal that is output from DAC of Mono CODEC is sent to Line Out, Mono Out and ADC of Stereo CODEC.
* DAC full Scale Level: 0.6*AVDD [Vpp](1.98Vpp@3.3V) Full Scale level of DAC of Mono CODEC is the same as that of ADC of Stereo CODEC.
MICL bit
AK4641
Microphone IPGA with ALC
ATT MICM bit ATT MICAD bit
Line Out through stereo mixer Mono Out
ADC of Stereo CODEC
Mic In 0dB/+20dB DAC2 bit AUX In
P
Bth Headset
Bluetooth Module
DAC of Mono CODEC
Figure 31. Path from DAC of Mono CODEC
MS0301-E-00 - 32 -
2004/05
ASAHI KASEI
[AK4641]
I2C-bus Control Interface
The AK4641 supports the fast-mode I2C-bus (max: 400kHz). 1. WRITE Operations Figure 32 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 38). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit (R/W). The most significant seven bits of the slave address are fixed as "0010010". If the slave address matches that of the AK4641, the AK4641 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 39). A R/W bit value of "1" indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4641. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 34). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 35). The AK4641 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 38). The AK4641 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4641 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1FH prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 40) except for the START and STOP conditions.
S T A R T
R/W="0"
S T O P Sub Address(n) Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P
SDA
Slave S Address A C K
Figure 32. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
1
0
R/W
Figure 33. The First Byte
0
0
0
A4
A3
A2
A1
A0
Figure 34. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 35. Byte Structure after the second byte
MS0301-E-00 - 33 -
2004/05
ASAHI KASEI
[AK4641]
(2)-2. READ Operations Set the R/W bit = "1" for the READ operation of the AK4641. After transmission of data, the master can read the next address's data by generating an acknowledge instead of generating a stop condition after the receipt of the first data word. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1FH prior to generating a stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4641 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. (2)-2-1. CURRENT ADDRESS READ The AK4641 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4641 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4641 ceases transmission.
S T A R T S T O P Data(n) A C K A C K Data(n+1) A C K Data(n+2) A C K A C K Data(n+x) A C K P
R/W="1"
SDA
Slave S Address
Figure 36. CURRENT ADDRESS READ (2)-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start request, a slave address (R/W bit = "0") and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to "1". The AK4641 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4641 ceases transmission.
S T A R T S T A R T Sub Address(n) A C K A C K
R/W="0"
R/W="1"
S T O P Data(n) Data(n+1) A C K A C K A C K Data(n+x) A C K P
SDA
Slave S Address
Slave S Address A C K
Figure 37. RANDOM ADDRESS READ
MS0301-E-00 - 34 -
2004/05
ASAHI KASEI
[AK4641]
SDA
SCL S start condition P stop condition
Figure 38. START and STOP Conditions
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement
1
2
8
9
START CONDITION
Figure 39. Acknowledge on the I2C-Bus
SDA
SCL
data line stable; data valid
change of data allowed
Figure 40. Bit Transfer on the I2C-Bus
MS0301-E-00 - 35 -
2004/05
ASAHI KASEI
[AK4641]
Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H Register Name Power Management 1 Power Management 2 Signal Select1 Signal Select2 Mode Control 1 Mode Control 2 DAC Control MIC Control Timer Select ALC Mode Control 1 ALC Mode Control 2 Input PGA Control Lch Digital ATT Control Rch Digital ATT Control Volume Control Status EQ Control 250Hz/100Hz EQ Control 3.5kHz/1kHz EQ Control 10kHz BT I/F CODEC Control D7 PMVCM MCKPD MOGN DACL 0 0 0 0 0 0 0 0 ATTL7 ATTR7 ATTM 0 EQB3 EQD3 0 0 D6 0 0 PSMO 0 0 MCK1 TM 0 0 0 REF6 IPGA6 ATTL6 ATTR6 ATTS2 0 EQB2 EQD2 0
BTFMT1
D5 0 0 DACM AUXL 0 MCK0 SMUTE AUXAD ZTM1 ALC1 REF5 IPGA5 ATTL5 ATTR5 ATTS1 0 EQB1 EQD1 0
BTFMT0
D4 PMLO MCKAC MICM MICL 0 0 DATTC MPWRE ZTM0 ZELM REF4 IPGA4 ATTL4 ATTR4 ATTS0 0 EQB0 EQD0 0 DAC2
D3 PMMO PMMO2 0 0 0 0 0 MPWRI WTM1 LMAT1 REF3 IPGA3 ATTL3 ATTR3 GN3 0 EQA3 EQC3 EQE3 ADC2
D2 PMAUX 0 0 AUXSI 0 HPM EQ MICAD WTM0 LMAT0 REF2 IPGA2 ATTL2 ATTR2 GN2 0 EQA2 EQC2 EQE2 PMBIF
D1 PMMIC 0 0 PSLOL DIF1 LOOP DEM1 MSEL LTM1 RATT REF1 IPGA1 ATTL1 ATTR1 GN1 0 EQA1 EQC1 EQE1 PMDA2
D0 PMADC PMDAC PSMO2 PSLOR DIF0 0 DEM0 MGAIN LTM0 LMTH REF0 IPGA0 ATTL0 ATTR0 GN0 DTMIC EQA0 EQC0 EQE0 PMAD2
*PDN pin = "L" resets the registers to their default values. *Unused bits must contain a "0" value. *Only write to address 00H to 13H.
MS0301-E-00 - 36 -
2004/05
ASAHI KASEI
[AK4641]
Addr 00H
Register Name Power Management 1 R/W Default
D7
PMVCM
R/W 0
D6 0 RD 0
D5 0 RD 0
D4 PMLO R/W 0
D3 PMMO R/W 0
D2 PMAUX R/W 0
D1 PMMIC R/W 0
D0 PMADC R/W 0
PMADC: ADC Block of Stereo CODEC Power Control 0: Power down (Default) 1: Power up When PMADC bit changes from "0" to "1", initializing cycle (2081/fs=47.2ms@44.1kHz) starts. After initializing cycle, digital data of the ADC of Stereo CODEC is output. PMMIC: MIC In Block Power Control 0: Power down (Default) 1: Power up PMMO: Mono Out Power Control 0: Power down (Default) 1: Power up PMLO: Line Out Power Control 0: Power down (Default) 1: Power up PMAUX: AUX In Power Control 0: Power down (Default) 1: Power up PMVCM: VCOM Block Power Control 0: Power down (Default) 1: Power up
MS0301-E-00 - 37 -
2004/05
ASAHI KASEI
[AK4641]
Addr 01H
Register Name Power Management 2 R/W Default
D7 MCKPD
R/W 1
D6 0 RD 0
D5 0 RD 0
D4
MCKAC
R/W 0
D3 PMMO2 R/W 0
D2 0 RD 0
D1 0 RD 0
D0 PMDAC R/W 0
PMDAC: DAC Block of Stereo CODEC Power Control 0: Power down (Default) 1: Power up PMMO2: Mono Out2 Power Control 0: Power down (Default) 1: Power up MCKAC: Master Clock input Mode Select 0: C-MOS input (Default) 1: AC-Coupling input MCKPD: MCLK Input Buffer Control 0: Enable 1: Disable (Default) When MCLK input with AC coupling is stopped, MCKPD bit should be set to "1". ADC and DAC of 16bit Stereo CODEC are powered-down at MCKPD bit = "1".
Note) The stereo mixer block (PMMIX) is powered down automatically. PMLO=PMMO2=PMAD2 bits = "0": Power Down Others: Power Up Each block can be powered down respectively by writing "0" in each bit. When the PDN pin is "L", all blocks are powered down. When all bits except MCKPD bit are "0" in the 00H and 01H addresses, all blocks are powered down. The register values remain unchanged. IPGA gain is reset when PMMIC bit is "0" (refer to the IPGA6-0 bits description). When any of the blocks are powered up, the PMVCM bit must be set to "1". MCLK, BICK and LRCK must always be present unless PMMIC=PMADC=PMDAC bits = "0" or PDN pin = "L". BBICK and BSYNC must always be present unless PMAD2=PMDA2=PMBIF bits = "0" or PDN pin = "L".
MS0301-E-00 - 38 -
2004/05
ASAHI KASEI
[AK4641]
Addr 02H
Register Name Signal Select1 R/W Default
D7
MOGN
R/W 0
D6 PSMO R/W 0
D5 DACM R/W 0
D4 MICM R/W 0
D3 0 RD 0
D2 0 RD 0
D1 0 RD 0
D0 PSMO2 R/W 0
PSMO2: Select mono output 2 of MOUT2 pin (Mixing = (L+R)/2) 0: Power Save Mode. Output VCOM voltage. (Default) 1: Normal Operation (Note) Hi-Z is output at PMMO2 bit = "0". MICM: Switch Control from Mic In to Mono Mixer 0: OFF (Default) 1: ON DACM: Switch Control from DAC of Stereo CODEC to Mono Mixer (Mixing = (L+R)/2) 0: OFF (Default) 1: ON PSMO: Select mono output of MOUT+/- pins 0: Power Save Mode. Output VCOM voltage. (Default) 1: Normal Operation (Note) Hi-Z is output at PMMO bit = "0". MOGN: Gain control for mono output 0: +6dB (Default) 1: -17dB
MS0301-E-00 - 39 -
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ASAHI KASEI
[AK4641]
Addr 03H
Register Name Signal Select2 R/W Default
D7 DACL R/W 1
D6 0 RD 0
D5 AUXL R/W 0
D4 MICL R/W 0
D3 0 RD 0
D2 AUXSI R/W 0
D1 PSLOL R/W 0
D0 PSLOR R/W 0
PSLOR: Select Rch Line output of ROUT pin 0: Power Save Mode. Output VCOM voltage. (Default) 1: Normal Operation (Note) Hi-Z is output at PMLO bit = "0". PSLOL: Select Lch Line output of LOUT pin 0: Power Save Mode. Output VCOM voltage. (Default) 1: Normal Operation (Note) Hi-Z is output at PMLO bit = "0". MICL: Switch Control from Mic In to Stereo Mixer 0: OFF (Default) 1: ON AUXL: Switch Control from AUX IN to Stereo Mixer 0: OFF (Default) 1: ON DACL: Switch Control from DAC of Stereo CODEC to Stereo Mixer 0: OFF 1: ON (Default) AUXSI: Select AUX Input 0: Differential Input (Default) 1: Single-ended Input. AUXIN+ pin is used for AUX input and AUXIN- pin is not available.
Addr 04H
Register Name Mode Control 1 R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4 0 RD 0
D3 0 RD 0
D2 0 RD 0
D1 DIF1 R/W 1
D0 DIF0 R/W 0
DIF1-0: Digital Audio Interface Format Select (See Table 5.)
Addr 05H
Register Name Mode Control 2 R/W Default
D7 0 RD 0
D6 MCK1 R/W 0
D5 MCK0 R/W 0
D4 0 RD 0
D3 0 RD 0
D2 HPM R/W 0
D1 LOOP R/W 0
D0 0 RD 0
LOOP: Loopback ON/OFF 0: OFF (Default) 1: ON ADC output data of Stereo CODEC is inputted to both Lch and Rch of DAC of Stereo CODEC. HPM: Mono output select from DAC of Stereo CODEC 0: Stereo (Default) 1: Mono. (L+R)/2 signal is output from Lch and Rch of DAC of Stereo CODEC MCK1-0: Input Master Clock Select (See Table 2.)
MS0301-E-00 - 40 -
2004/05
ASAHI KASEI
[AK4641]
Addr 06H
Register Name DAC Control R/W Default
D7 0 RD 0
D6 TM R/W 0
D5 SMUTE R/W 0
D4 DATTC R/W 1
D3 0 RD 0
D2 EQ R/W 0
D1 DEM1 R/W 0
D0 DEM0 R/W 1
DEM1-0: De-emphases response (See Table 12.) EQ: Select 5 Band Equalizer. 0: OFF (Default) 1: ON DATTC: DAC of Stereo CODEC Digital Attenuator Control Mode Select 0: ATTL6-0 and ATTR6-0 bits control attenuator level of Lch and Rch respectively. 1: ATTL6-0 bits control both Lch and Rch at same time. (Default) When DATTC bit = "1", the value of ATTR6-0 does not change. SMUTE: Soft Mute Control 0: Normal Operation (Default) 1: DAC outputs of Stereo CODEC soft-muted TM: Soft Mute and DATT Transition Time Select (See Table 15.)
Addr 07H
Register Name MIC Control R/W Default
D7 0 RD 0
D6 0 RD 0
D5
AUXAD
D4
MPWRE
D3
MPWRI
D2
MICAD
D1
MSEL
D0
MGAIN
R/W 0
R/W 0
R/W 0
R/W 1
R/W 0
R/W 1
MGAIN: 1st Mic Amp Gain control 0: OFF. 0dB 1: ON. +20dB (Default) MSEL: Microphone select 0: Internal Mic (Default) 1: External Mic MICAD: Switch Control from Mic In to ADC of Stereo CODEC 0: OFF 1: ON (Default) MPWRI: Power Supply Control for Internal Microphone 0: OFF (Default) 1: ON MPWRE: Power Supply for External Microphone 0: OFF (Default) 1: ON
MS0301-E-00 - 41 -
2004/05
ASAHI KASEI
[AK4641]
AUXAD: Switch Control from AUX In to ADC of Stereo CODEC 0: OFF (default) 1: ON
Addr 08H
Register Name Timer Select R/W Default
D7 0 RD 0
D6 0 RD 0
D5 ZTM1 R/W 0
D4 ZTM0 R/W 0
D3 WTM1 R/W 0
D2 WTM0 R/W 0
D1 LTM1 R/W 0
D0 LTM0 R/W 0
LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = "1") The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by the period specified by LTM1-0 bits. LTM1 ALC1 Limiter Operation Period 8kHz 16kHz 44.1kHz Default 0 0 0.5/fs 31s 11s 63s 0 1 1/fs 125s 63s 23s 1 0 2/fs 125s 45s 250s 1 1 4/fs 250s 91s 500s Table 17. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit = "1") LTM0
WTM1-0: ALC1 Recovery Waiting Period WTM1-0 bits set a period of recovery operation when any limiter operation does not occur during ALC1 operation. When the output signal level exceeds auto recovery waiting counter reset level set by LMTH bit, the auto recovery waiting counter is reset. The waiting timer starts when the output signal level becomes below the auto recovery waiting counter reset level. WTM1 0 0 1 1 WTM0 0 1 0 1 ALC1 Recovery Operation Waiting Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 18. ALC1 Recovery Operation Waiting Period
Default
ZTM1-0: Zero crossing timeout at the write operation by P, ALC1 recovery operation and zero crossing enable (ZELM bit = "0") of the ALC1 operation When IPGA of each L/R channels perform zero crossing or timeout independently, the IPGA value is changed by P WRITE operation or ALC1 recovery operation or ALC1 limiter operation (ZELM bit = "0"). ZTM1 0 0 1 1 ZTM0 0 1 0 1 Zero Crossing Timeout Period 8kHz 16kHz 128/fs 16ms 8ms 256/fs 32ms 16ms 512/fs 64ms 32ms 1024/fs 128ms 64ms Table 19. Zero Crossing Timeout Period
44.1kHz 2.9ms 5.8ms 11.6ms 23.2ms
Default
MS0301-E-00 - 42 -
2004/05
ASAHI KASEI
[AK4641]
Addr 09H
Register Name ALC Mode Control 1 R/W Default
D7 0 RD 0
D6 0 RD 0
D5 ALC1 R/W 0
D4 ZELM R/W 0
D3 LMAT1 R/W 0
D2 LMAT0 R/W 0
D1 RATT R/W 0
D0 LMTH R/W 0
LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about 2dB. LMTH 0 1
ALC1 Limiter Detection Level ALC1 Recovery Waiting Counter Reset Level
-6.0dB > ADC Input -8.0dBFS ADC Input -6.0dBFS -4.0dB > ADC Input -6.0dBFS ADC Input -4.0dBFS Table 20. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
Default
RATT: ALC1 Recovery GAIN Step During the ALC1 Recovery operation, the number of steps changed from current IPGA value is set. For example, when the current IPGA value is "30H" and RATT bit = "1" is set, IPGA changes to "32H" by the ALC1 recovery operation, the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the reference level (REF6-0 bits), the IPGA value does not increase. RATT GAIN STEP 0 1 Default 1 2 Table 21. ALC1 Recovery Gain Step Setting LMAT1-0: ALC1 Limiter ATT Step During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level set by LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value is 47H and the LMAT1-0 bits = "11", the IPGA transition to "43H" when the ALC1 limiter operation starts, resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA = "00H" (-8dB), it clips to "00H". LMAT1 LMAT0 ATT STEP 0 0 1 Default 0 1 2 1 0 3 1 1 4 Table 22. ALC1 Limiter ATT Step Setting ZELM: Enable zero crossing detection at ALC1 Limiter operation 0: Enable (Default) 1: Disable When the ZELM bit = "0", the IPGA of each L/R channel perform a zero crossing or timeout independently and the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery operation. When the ZELM bit = "1", the IPGA value is changed immediately. ALC1: ALC1 Enable 0: ALC1 Disable (Default) 1: ALC1 Enable
MS0301-E-00 - 43 -
2004/05
ASAHI KASEI
[AK4641]
Addr 0AH
Register Name ALC Mode Control 2 R/W Default
D7 0 RD 0
D6 REF6 R/W 0
D5 REF5 R/W 1
D4 REF4 R/W 1
D3 REF3 R/W 0
D2 REF2 R/W 1
D1 REF1 R/W 1
D0 REF0 R/W 0
REF6-0: Set the Reference value at ALC1 Recovery Operation During the ALC1 recovery operation, if the IPGA value exceeds the setting reference value by gain operation, then the IPGA does not become larger than the reference value. For example, when REF6-0 bits = "30H", RATT = 2step, IPGA = "2FH", even if the input signal does not exceed the "ALC1 Recovery Waiting Counter Reset Level", the IPGA does not change to "2FH" + 2step = "31H", but keeps "30H". Default is "36H".
REF6-0 GAIN (dB) STEP 47H +27.5 46H +27.0 45H +26.5 : : 36H +19.0 Default : : 10H +0.0 : : 0.5dB 06H -5.0 05H -5.5 04H -6.0 03H -6.5 02H -7.0 01H -7.5 00H -8.0 Table 23. Setting Reference Value at ALC1 Recovery Operation
Addr 0BH
Register Name Input PGA Control R/W Default
D7 0 RD 0
D6 IPGA6 R/W 0
D5 IPGA5 R/W 0
D4 IPGA4 R/W 1
D3 IPGA3 R/W 0
D2 IPGA2 R/W 0
D1 IPGA1 R/W 0
D0 IPGA0 R/W 0
IPGA6-0: Input Analog PGA (See Table 7.) When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is "1" and ALC1 bit is "0". IPGA gain is reset when PMMIC bit is "0", and then IPGA operation starts from the default value when PMMIC is changed to "1". When ALC1 bit is changed from "1" to "0", IPGA holds the last gain value set by ALC1 operation. When IPGA6-0 bits are read, the register values written by the last write operation is read out regardless the actual gain.
Addr 0CH 0DH Register Name Lch Digital ATT Control Rch Digital ATT Control R/W Default D7 ATTL7 ATTR7 R/W 0 D6 ATTL6 ATTR6 R/W 0 D5 ATTL5 ATTR5 R/W 0 D4 ATTL4 ATTR4 R/W 0 D3 ATTL3 ATTR3 R/W 0 D2 ATTL2 ATTR2 R/W 0 D1 ATTL1 ATTR1 R/W 0 D0 ATTL0 ATTR0 R/W 0
ATTL/R7-0: Digital ATT Output Control These bits control the attenuation level of DAC output of Stereo CODEC. Step size of ATT is approximately 0.5dB (See Table 13). Note) Even if DATTC bit = "1", ATTR7-0 bits are not changed when the ATTL7-0 bits are written.
MS0301-E-00 - 44 -
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ASAHI KASEI
[AK4641]
Addr 0EH
Register Name Volume Control R/W Default
D7 ATTM R/W 0
D6 ATTS2 R/W 1
D5 ATTS1 R/W 0
D4 ATTS0 R/W 1
D3 GN3 R/W 0
D2 GN2 R/W 1
D1 GN1 R/W 1
D0 GN0 R/W 1
GN3-0: Volume of AUX In (see Table 16.) ATTS2-0: Attenuator select of signal from Mic IN to Stereo Mixer (See Table 8.) ATTM: Attenuator control for signal from Mic IN to Mono Mixer 0: 0dB (Default) 1: -4dB
Addr 0FH
Register Name Status R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4 0 RD 0
D3 0 RD 0
D2 0 RD 0
D1 0 RD 0
D0 DTMIC RD 0
DTMIC: Microphone Detection Result 0: Microphone is not detected. (Default) 1: Microphone is detected.
Addr 10H 11H
Register Name EQ Control 250Hz/100Hz EQ Control 3.5kHz/1kHz R/W Default Register Name EQ Control 10kHz R/W Default
D7 EQB3 EQD3 R/W 1 D7 0 RD 0
D6 EQB2 EQD2 R/W 0 D6 0 RD 0
D5 EQB1 EQD1 R/W 0 D5 0 RD 0
D4 EQB0 EQD0 R/W 0 D4 0 RD 0
D3 EQA3 EQC3 R/W 1 D3 EQE3 R/W 1
D2 EQA2 EQC2 R/W 0 D2 EQE2 R/W 0
D1 EQA1 EQC1 R/W 0 D1 EQE1 R/W 0
D0 EQA0 EQC0 R/W 0 D0 EQE0 R/W 0
Addr 12H
EQA3-0: Select the boost level of 100Hz EQB3-0: Select the boost level of 250Hz EQC3-0: Select the boost level of 1kHz EQD3-0: Select the boost level of 3.5kHz EQE3-0: Select the boost level of 10kHz See Table 14.
MS0301-E-00 - 45 -
2004/05
ASAHI KASEI
[AK4641]
Addr 13H
Register Name BT I/F CODEC Control R/W Default
D7 0 RD 0
D6
BTFMT1
D5
BTFMT0
R/W 0
R/W 0
D4 DAC2 R/W 0
D3 ADC2 R/W 1
D2 PMBIF R/W 0
D1 PMDA2 R/W 0
D0 PMAD2 R/W 0
PMAD2: ADC Block of Mono CODEC Power Control 0: Power down (Default) 1: Power up PMDA2: DAC Block of Mono CODEC Power Control 0: Power down (Default) 1: Power up PMBIF: 16bit Mono Interface and PLL Block Power Control 0: Power down (Default) 1: Power up ADC and DAC of 16bit Mono CODEC are powered-down at PMBIF bit = "0". AD2: Select Signal that is input to ADC of 16bit Mono CODEC 0: OFF 1: ON (Default) DAC2: Select DAC of Mono CODEC signal (See Figure 21.) 0: MIC Input Signal (Default) 1: DAC signal of Mono CODEC BTFMT1-0: Digital Audio Interface Format Select for 16bit Mono CODEC (See Table 6.)
MS0301-E-00 - 46 -
2004/05
ASAHI KASEI
[AK4641]
SYSTEM DESIGN
Figure 41 shows the system connection diagram for t the AK4641.
1 EXT 36 MDT 35 MICOUT 34
1 AIN 33
1
1
C
C
C
AUXIN+ 32
AUXIN- 31
MOUT+ 30
MOUT- 29
2.2k 1 MPE 2.2k 2 MPI 1 3 INT 0.1 0.1 6 AVDD 7 PVDD 10 0.1 8 PVSS 5.1k 470n 9 VCOC 4 VCOM 5 AVSS 10
LOUT 28
ROUT 27 MOUT2 26 TST2 25 BBICK 24
C C
2.2 Analog Supply 2.6~ 3.6V
Top View
18 MCLK 15 SDTO 16 LRCK 11 TST1 17 BICK 14 SDTI 10 PDN 13 SDA 12 SCL
BSYNC 23 BSDTO 22 BSDTI 21 DVSS 20 0.1 DVDD 19
Bluetooth Proccesor
10
Reset
DSP and uP
Notes: - AVSS, DVSS and BVSS of the AK4641 should be distributed separately from the ground of external controllers. - Values of R and C in Figure 41 should depend on system. - All digital input pins should not be left floating. Figure 41. Typical Connection Diagram
MS0301-E-00 - 47 -
2004/05
ASAHI KASEI
[AK4641]
1. Grounding and Power Supply Decoupling
The AK4641 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and BVDD are usually supplied from the system's analog supply. If AVDD, DVDD and BVDD are supplied separately, the power up sequence is not critical. AVSS, DVSS and BVSS of the AK4641 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4641 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2F electrolytic capacitor in parallel with a 0.1F ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the AVDD and VCOM pins in order to avoid unwanted coupling into the AK4641.
3. Analog Inputs
The AK4641 has the 16bit Mono CODEC to connect with Bluetooth Module that supports 8kHz to 16kHz sample rate. The AK4641 includes PLL that generate the master clock for Mono CODEC from input BSYNC signal. The PLL should be powered-up after BSYNC signal is inputted. The PLL needs 90ms (max) lock time, when the PLL is powered-up (PMBIF bit = "0" "1"). The Mic inputs are single-ended. AUX input is differential. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic input, 0.6 x AVDD Vpp for AUX input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2RC). The AK4641 can accept input voltages from AVSS to AVDD.
4. Analog Outputs
The input data format for the DAC of both Stereo and Mono CODEC is 2's complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Mono output from the MOUT2 pin, Mono Line Output from the MOUT+/MOUT- pins and Stereo Line Out from the LOUT/ROUT pins are centered at 0.45 x AVDD.
MS0301-E-00 - 48 -
2004/05
ASAHI KASEI
[AK4641]
PACKAGE
36pin QFN (Unit: mm) 6.20 0.1
2 0.
6.00 0.05
27 19
0.60 0.01 19 18 27
2 05 0. 11 0.
28
18
28
0 38 .4
6.00 0.05
6.20 0.1
45
45
34 0. 11 0.
36 1 9
10 3 - C0.5
10
36 9 1 0.50 0.22 0.05 0.05
M
C0.7
0.22 0.05
0.05
Note) The part of black at four corners on reverse side must not be soldered and must be open.
Material & Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate (Pb free)
MS0301-E-00 - 49 -
0.02+0.02 -0.015
0.90 0.05
2004/05
ASAHI KASEI
[AK4641]
MARKING
AKM 4641VN
XXXXXXX
1
XXXXXXX : Date code identifier (7 digits)
Revision History
Date (YY/MM/DD) 04/05/17 Revision 00 Reason First Edition Page Contents
MS0301-E-00 - 50 -
2004/05
ASAHI KASEI
[AK4641]
IMPORTANT NOTICE
* These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0301-E-00 - 51 -
2004/05

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